The present invention relates to a semiconductor memory device, and to a technique which is particularly effective when applied to a memory system for multivalued information in a nonvolatile semiconductor memory device. By way of example, the technique is effective when utilized for a nonvolatile memory device (hereinafter referred to simply as a flash memory) in which a plurality of pieces of stored information can be electrically erased all at once.
In a flash memory, nonvolatile memory elements each having a control gate and a floating gate are used as memory cells, and each memory cell can be constructed of a single transistor. In such a flash memory, when a write operation is executed, as illustrated in FIG. 10, the drain region of the nonvolatile memory element is set at, for example, about 5 V (volts), while a word line with the control gate CG connected thereto is set at, for example, about −11 V, whereby electric charges are extracted from the floating gate FG by means of a tunnel current so as to render the threshold voltage of the memory element low (logical value “0”). When an erase operation is executed, as illustrated in FIG. 11, a well region, the drain region and a source region are set at about −4 V, by way of example, while the control gate CG is set at a high voltage, such as 12 V, whereby negative charges are injected into the floating gate FG by the generation of a tunnel current so as to render the threshold voltage high (logical value “1”). Thus, data of 1 (one) bit is stored in one memory cell.
There has been proposed the concept of a so-called “multivalued” memory wherein data of 2 or more bits is stored in one memory cell for the purpose of enlarging the memory capacity. An invention concerning such a multivalued memory is disclosed in, for example, PCT/JP95/02260.